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| this is information on a product in full production. april 2015 docid027739 rev 1 1/72 a6986f 38 v 1.5 a synchronous step-down switching regulator with 30 a quiescent current datasheet - production data features ? aecq100 qualification ? 1.5 a dc output current ? 4 v to 38 v operating input voltage ? low consumption mode or low noise mode ? 30 a i q at light-load (lcm v out = 3.3 v) ? 8 a i q-shtdwn ? adjustable f sw (250 khz - 2 mhz) ? fixed output voltage (3.3 v and 5 v) or adjustable from 0.85 v to v in ? embedded output voltage supervisor ? synchronization ? adjustable soft-start time ? internal current limiting ? overvoltage protection ? output voltage sequencing ? peak current mode architecture ? r dson hs = 180 m ? , r dson ls = 150 m ? ? thermal shutdown applications ? designed for automotive systems ? battery powered applications ? car body applications (lcm) ? car audio and low noise applications (lnm) description the a6986f automotive grade device is a step- down monolithic switchin g regulator able to deliver up to 1.5 a dc. the output voltage adjustability ranges from 0.85 v to vin. the 100% duty cycle capability an d the wide input voltage range meet the cold crank and load dump specifications for automo tive systems. the ?low consumption mode? (l cm) is designed for applications active during car parking, so it maximizes the efficiency at light-load with controlled output voltage ripple. the ?low noise mode? (lnm) makes the switching frequency constant and minimizes the output voltage ripple overload current range, meeting the low noise application specification like car audio. the output voltage supervisor manages the reset phase for any digital load (c, fpga.). the rst open collector output can also implement output voltage sequencing during the power-up phase. the synchronous rectification, designed for high efficiency at medium - heavy load, and the high switching frequency capab ility make the size of the application compact. pulse by pulse current sensing on both power elements implements an effective constant current protection. htssop16 (r th = 40 c/w) www.st.com
contents a6986f 2/72 docid027739 rev 1 contents 1 application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.3 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.4 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.5 esd protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 datasheet parameters over the temperatur e range . . . . . . . . . . . . . . . 13 5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1 power supply and voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 switchover feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2 voltages monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.3 soft-start and inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.3.1 ratiometric startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.3.2 output voltage sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.4 error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.5 light-load operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.5.1 low noise mode (lnm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.5.2 low consumption mode (lcm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.6 switchover feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.6.1 lcm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.6.2 lnm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.7 overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 ocp and switchover feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.8 overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.9 thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 docid027739 rev 1 3/72 a6986f contents 72 6 closing the loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.1 g co (s) control to output transfer function . . . . . . . . . . . . . . . . . . . . . . . . 37 6.2 error amplifier compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.3 voltage divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.4 total loop gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.5 compensation network design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.1 output voltage adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.2 switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.3 mlf pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.4 voltage supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.5 synchronization (lnm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.6 design of the power components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.6.1 input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.6.2 inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 7.6.3 output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 8 application board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9 efficiency curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 10 emc testing results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 11 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 htssop16 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 12 order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 13 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 application schematic a6986f 4/72 docid027739 rev 1 1 application schematic figure 1. application schematic t j h o b m ( / % 1 8 3 h o e 1 8 3 h o e v $ 3 4 5 " ' " ' 7 # * " 4 3 4 5 7 $ $ 4 4 * / ) 4 : / $ ) ' 4 8 . - ' $ 0 . 1 % & - " : ' # 4 ( / % 1 ( / % 1 ( / % - 9 - 9 7 * / & 1 v ' v ' 7 0 6 5 7 0 6 5 o ' o ' ( / % ( / % o ' o ' v ' v ' ( / % ( / % v ) v ) v ' v ' o ' o ' . . l l 7 * / 7 * / q q docid027739 rev 1 5/72 a6986f pin settings 72 2 pin settings 2.1 pin connection figure 2. pin connection (top view) 2.2 pin description 3 4 5 7 $ $ 4 4 * / ) 4 : / $ ) * 4 , * 1 ' 4 8 . - ' $ 0 . 1 % & - " : 7 # * " 4 7 * / - 9 - 9 1 ( / % 1 ( / % 4 ( / % 7 0 6 5 & 9 1 0 4 & % 1 " % 5 0 4 ( / % 1 ( / % table 1. pin description no. pin description 1rst the rst open collector output is driven low when th e output voltage is out of regulation. the rst is released after an adjustable time delay once the output voltage is over the active delay threshold. 2vcc connect a ceramic capacitor ( 470 nf) to filter internal voltage reference. this pin supplies the embedded analog circuitry. 3 ss/inh an open collector stage can disable the device clamping this pin to gnd (inh mode). an internal current generator (2 ? a typ.) charges the external capaci tor to implement the soft-start. 4 synch/ iskp the pin features master / slave synchronization in lnm (see section 5.5.1 on page 25 ) and skip current level selection in lcm (see section 5.5.2 on page 25 ). 5fsw a pull up resistor (e24 series only) to vcc or pull down to gnd selects the switching frequency. pinstrapping is active only before the soft-sta rt phase to minimize the ic consumption. 6mlf a pull up resistor (e24 series only) to vcc or pull down to gnd selects the low noise mode/low consumption mode and the active rst threshold. pi nstrapping is active only before the soft-start phase to minimize the ic consumption. 7 comp output of the error amplifier. the designed compensation network is connected at this pin. 8delay an external capacitor connected at this pin sets the time delay to assert the rising edge of the rst o.c. after the output voltage is over the reset th reshold. if this pin is left floating, rst is like a power good. 9 vout output voltage sensing 10 sgnd signal gnd 11 pgnd power gnd pin settings a6986f 6/72 docid027739 rev 1 2.3 maximum ratings stressing the device ab ove the rating listed in table 2: absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions may affect device reliability. 12 pgnd power gnd 13 lx switching node 14 lx switching node 15 vin dc input voltage 16 v bias typically connected to the regulat ed output voltage. an external volt age reference can be used to supply part of the analog circuitry to increase th e efficiency at light-load. connect to gnd if not used. - e. p. exposed pad must be connected to sgnd, pgnd table 1. pin description (continued) no. pin description table 2. absolute maximum ratings symbol description min. max. unit v in see table 1 -0.3 40 v delay -0.3 v cc + 0.3 v pgnd sgnd - 0.3 sgnd + 0.3 v sgnd v v cc -0.3 (v in + 0.3) or (max. 4) v ss / inh -0.3 v in + 0.3 v mlf -0.3 v cc + 0.3 v comp -0.3 v cc + 0.3 v vout -0.3 10 v fsw -0.3 v cc + 0.3 v synch -0.3 v in + 0.3 v v bias -0.3 (v in + 0.3) or (max. 6) v rst -0.3 v in + 0.3 v lx -0.3 v in + 0.3 v t j operating temperature range -40 150 c t stg storage temperature range -65 to 150 c t lead lead temperature (soldering 10 sec.) 260 c i hs , i ls high-side / low-side switch current 2 a docid027739 rev 1 7/72 a6986f pin settings 72 2.4 thermal data 2.5 esd protection table 3. thermal data symbol parameter value unit r th ja thermal resistance junction ambi ent (device soldered on the stmicroelectronics ? demonstration board) 40 c/w table 4. esd protection symbol test condition value unit esd hbm 2 kv mm 200 v cdm 500 v electrical characteristics a6986f 8/72 docid027739 rev 1 3 electrical characteristics t j = -40 to 135 c, v in = 12 v unless otherwise specified. table 5. electrical characteristics symbol parameter test condit ion note min. typ. max. unit v in operating input voltage range 4 38 v v inh v cc uvlo rising threshold 2.7 3.5 v inl v cc uvlo falling threshold 2.4 3.5 i pk peak current limit duty cycle < 20% 2.3 a duty cycle = 100% closed loop operation 1.8 i vy valley current limit 2.4 i skiph programmable skip current limit lcm, v synch = gnd (1) 0.2 0.4 0.6 i skipl lcm, v synch = vcc (2) 0.2 i vy_snk reverse current limit lnm or v out overvoltage 0.5 1 2 r dson hs high-side rdson i sw = 1 a 0.18 0.360 ? r dson ls low-side rdson i sw = 1 a 0.15 0.300 f sw selected switching frequency fsw pinstrapping before ss see table 6: f sw selection i fsw fsw biasing current ss ended 0 500 na lcm/lnm low noise mode / low consumption mode selection mlf pinstrapping before ss see table 7 on page 11 , table 8 on page 12 , table 9 on page 12 i mlf mlf biasing current ss ended 0 500 na d duty cycle (2) 0 100 % t on min minimum on time 80 ns vcc regulator v cc ldo output voltage v bias = gnd (no switchover) 2.9 3.3 3.6 v v bias = 5 v (switchover) 2.9 3.3 3.6 swo v bias threshold (3 v< v bias < 5.5 v) switch internal supply from v in to v bias 2.85 3.2 switch internal supply from v bias to v in 2.78 3.15 power consumption i shtdwn shutdown current from v in v ss/inh = gnd 4 8 15 ? a docid027739 rev 1 9/72 a6986f electrical characteristics 72 i q opvin quiescent current from v in lcm - swo v ref < v fb < v ovp (sleep) v bias = 3.3 v (3) 41015 ? a lcm - no swo v ref < v fb < v ovp (sleep) v bias = gnd (3) 35 70 120 lnm - swo v fb = gnd (no sleep) v bias = 3.3 v 0.5 1.5 5 ma lnm - no swo v fb = gnd (no sleep) v bias = gnd 22.8 6 i q opvbias quiescent current from v bias lcm - swo v ref < v fb < v ovp (sleep) v bias = 3.3 v (3) 25 50 115 ? a lnm - swo v fb = gnd (no sleep) v bias = 3.3 v 0.5 1.2 5 ma soft-start v inh vss threshold ss rising 200 460 700 mv v inh hyst vss hysteresis 100 140 i ss ch c ss charging current v ss < v inh or t < t ss setup or v ea+ > v fb (2) 1 ? a t > t ss setup and v ea+ < v fb (2) 4 v ss start start of internal error amplifier ramp 0.995 1.1 1.150 v ss gain ss/inh to internal error amplifier gain 3 error amplifier v out voltage feedback 3.3 v (a69863v3) 3.25 3.3 3.35 v 5 v (a69865v) 4.925 5.0. 5.075 i vout vout biasing current 3.3 v (a69863v3) 4 6 8.5 ? a 5 v (a69865v) 7.5 10 13.5 a v error amplifier gain (2) 100 db i comp ea output current capability 6 12 25 ? a (4) 4 table 5. electrical ch aracteristics (continued) symbol parameter test condit ion note min. typ. max. unit electrical characteristics a6986f 10/72 docid027739 rev 1 inner current loop g cs current sense transconductance (v comp to inductor current gain) ipk = 1 a (2) 2.5 a/v slope compensation (5) 0.45 0.75 1 a overvoltage protection v ovp overvoltage trip (v ovp /v ref ) 1.15 1.2 1.25 v ovp hyst overvoltage hysteresis 0.5 2 5 % synchronization (fan out: 6 slave devices typ.) f syn min synchronization frequency lnm; f sw = vcc 266.5 khz v syn th synch input threshold lnm, synch rising 0.70 1.2 v i syn synch pull-down current lnm, v syn = 1.2 v 0.7 ma v syn out high level output lnm, 5 ma sinking load 1.40 v low level output lnm, 0.7 ma sourcing load 0.6 reset v thr selected rst threshold mlf pinstrapping before ss see ta ble 7 , ta ble 8 , table 9 v thr hyst rst hysteresis (2) 2% v rst rst open collector output v in > v inh and v fb < v th 4 ma sinking load 0.4 v 2 < v in < v inh 4 ma sinking load 0.8 delay v thd rst open collector released as soon as v delay > v thd v fb > v thr 1.19 1.23 4 1.258 v i d ch c delay charging current v fb > v thr 12 3 ? a thermal shutdown t shdwn thermal shutdown temperature (2) 165 c t hys thermal shutdown hysteresis (2) 30 1. parameter tested in static condition during testing phase. parameter value may change over dynamic application condition. 2. not tested in production. 3. lcm enables sleep mode at light-load. 4. t j = -40 c. 5. measured at f sw = 250 khz. table 5. electrical ch aracteristics (continued) symbol parameter test condit ion note min. typ. max. unit v pp g cs ? docid027739 rev 1 11/72 a6986f electrical characteristics 72 t j = -40 to 135 c, v in = 12 v unless otherwise specified. table 6. f sw selection t j = -40 to 135 c, v in = 12 v unless otherwise specified. table 7. lnm / lcm selection (a6986f3v3) symbol r vcc (e24 series) r gnd (e24 series) tj f sw min. f sw typ. f sw max. unit f sw 0 ? nc 225 250 275 khz 1.8 k ? nc (1) 1. not tested in production. 285 3.3 k ? nc 330 5.6 k ? nc 380 10 k ? nc 435 nc 0 ? 450 500 550 18 k ? nc (1) 575 33 k ? nc 660 56 k ? nc 755 nc 1.8 k ? 870 nc 3.3 k ? 900 1000 1100 nc 5.6 k ? (1) 1150 nc 10 k ? 1310 nc 18 k ? 1500 nc 33 k ? 1575 1750 1925 nc 56 k ? 1800 2000 2200 symbol r vcc (e24 1%) r gnd (e24 1%) operating mode v rst /v out (tgt. value) v rst min. v rst typ. v rst max. unit v rst 0 ? nc lcm 93% 3.008 3.069 3.130 v 8.2 k ? nc 80% 2.587 2.640 2.693 18 k ? nc 87% 2.814 2.871 2.928 39 k ? nc 96% 3.105 3.168 3.231 nc 0 ? lnm 93% 3.008 3.069 3.130 nc 8.2 k ? 80% 2.587 2.640 2.693 nc 18 k ? 87% 2.814 2.871 2.928 nc 39 k ? 96% 3.105 3.168 3.231 electrical characteristics a6986f 12/72 docid027739 rev 1 t j = -40 to 135 c, v in = 12 v unless otherwise specified. table 8. lnm / lcm selection (a6986f5v) t j = -40 to 135 c, v in = 12 v unless otherwise specified. table 9. lnm / lcm selection (a6986f) symbol r vcc (e24 1%) r gnd (e24 1%) operating mode v rst /v out (tgt. value) v rst min. v rst typ. v rst max. unit v rst 0 ? nc lcm 93% 4.557 4.650 4.743 v 8.2 k ? nc 80% 3.920 4.000 4.080 18 k ? nc 87% 4.263 4.350 4.437 39 k ? nc 96% 4.704 4.800 4.896 nc 0 ? lnm 93% 4.557 4.650 4.743 nc 8.2 k ? 80% 3.920 4.000 4.080 nc 18 k ? 87% 4.263 4.350 4.437 nc 39 k ? 96% 4.704 4.800 4.896 symbol r vcc (e24 1%) r gnd (e24 1%) operating mode v rst /v out (tgt value) v rst min. v rst typ. v rst max. unit v rst 0 ? nc lcm 93% 0.779 0.791 0.802 v 8.2 k ? 1% nc 80% 0.670 0.680 0.690 18 k ? 1% nc 87% 0.728 0.740 0.751 39 k ? 1% nc 96% 0.804 0.816 0.828 nc 0 ? lnm 93% 0.779 0.791 0.802 nc 8.2 k ?? 1% 80% 0.670 0.680 0.690 nc 18 k ? 1% 87% 0.728 0.740 0.751 nc 39 k ? 1% 96% 0.804 0.816 0.828 docid027739 rev 1 13/72 a6986f datasheet parameters over the temperature range 72 4 datasheet parameters ov er the temperature range the 100% of the population in the production flow is tested at three different ambient temperatures (-40 c, +25 c, +135 c) to gu arantee the datasheet parameters inside the junction temperature range (-40 c, +135 c). the device operation is guaranteed when the junction temperature is inside the (-40 c, +150 c) temperature range. the desi gner can estimate the s ilicon temperature increase respect to the ambient temperature evaluating the internal power losses generated during the device operation. however the embedded thermal protection disabl es the switching activity to protect the device in case the junction temperature reaches the t shtdwn (+165 c typ.) temperature. all the datasheet parameters can be guarant eed to a maximum junction temperature of +135 c to avoid triggering the thermal shutdown protection during the testing phase because of self-heating. functional description a6986f 14/72 docid027739 rev 1 5 functional description the a6986f device is based on a ?peak curr ent mode?, constant frequency control. as a consequence, the intersection between the erro r amplifier output and the sensed inductor current generates the pwm control signal to drive the power switch. the device features lnm (low noise mode) th at is forced pwm control, or lcm (low consumption mode) to increase the efficiency at light-load. the main internal blocks shown in the block diagram in figure 3 are: ? embedded power elements. thanks to the p-channel mosfet as high-side switch the device features low dropout operation ? a fully integrated sa wtooth oscillator with adjustable frequency ? a transconductance error amplifier ? an internal feedback divider g div int ? the high-side current sense amplifier to sense the inductor current ? a ?pulse width modulator? (pwm) comparator and the driving circuitry of the embedded power elements ? the soft-start blocks to ramp the error ampl ifier reference voltage and so decreases the inrush current at power-up. the ss/inh pin inhibits the device when driven low. ? the switchover capability of the internal regu lator to supply a port ion of the quiescent current when the v bias pin is connected to an external output voltage ? the synchronization circuitry to manage master / slave operation and the synchronization to an external clock ? the current limitation circuit to implement the constant current protection, sensing pulse by pulse high-side / low-side switch current. in case of heavy short-circuit the current protection is fold back to decr ease the stress of the external components ? a circuit to implement the thermal protection function ? the ovp circuitry to discharge the output capacitor in case of overvoltage event ? mlf pin strapping sets the lnm/lcm mode and the thresholds of the rst comparator ? fsw pinstrapping sets the switching frequency ? the rst open collector output docid027739 rev 1 15/72 a6986f functional description 72 figure 3. internal block diagram 5.1 power supply an d voltage reference the internal regulator block consists of a st art-up circuit, the voltage pre-regulator that provides current to all the blocks and the b andgap voltage reference. the starter supplies the startup current when the input voltage g oes high and the device is enabled (ss/inh pin over the inhibits threshold). the pre-regulator block supplies the bandgap cell and the rest of the circuitry with a regulated voltage that has a very low supply voltage noise sensitivity. switchover feature the switchover scheme of the pre-regulator block features to derive th e main contribution of the supply current for the internal circui try from an external voltage (3 v < v bias < 5.5 v is typically connected to the regulated output volt age). this helps to decrease the equivalent quiescent curren t seen at v in . (please refer to section 5.6: switchover feature on page 31 ). 5.2 voltages monitor an internal block continuously senses the v cc , v bias and v bg . if the monitored voltages are good, the regulator starts operating. there is also a hysteresis on the v cc (uvlo). rst driver gnd gnd peak cl valley cl zero crossing loop control oscillator l.n. / l.c. rst th. lx vout e/a power p mos power n mos sense p mos sense n mos vcc slope vin sync comp gnd driver gnd gnd valley cl loop control e/a power p mos mos slope ovp + - mlf delay delay ss/inh ss/inh v ref 0 t ss + - fsw g div int functional description a6986f 16/72 docid027739 rev 1 figure 4. internal circuit 5.3 soft-start and inhibit the soft-start and inhibit features are multiplexed on the same pin. an internal current source charges the external soft-start capacitor to implement a voltage ramp on the ss/inh pin. the device is inhibited as long as the ss/inh pin voltage is lower than the v inh threshold and the soft-start takes place when ss/inh pin crosses v ss start . (see figure 5: soft-start phase ). the internal current generator sources 1 ? a typ. current when the voltage of the vcc pin crosses the uvlo threshold. the current increases to 4 ? a typ. as soon as the ss/inh voltage is higher than the v inh threshold. this feature helps to decrease the current consumption in inhibit mode. an external open collector can be used to set the inhibit operation clamping the ss/inh voltage below v inh threshold. the startup feature minimizes the inrush current and decreases the stress of the power components during the power-up phase. the ramp implemented on the reference of the error amplifier has a gain three times higher (ss gain ) than the external ramp present at ss/inh pin. 6 7 $ 5 7 ( 5 , & % , $ 6 3 5 ( 5 ( * 8 / $ 7 2 5 % $ 1 ' * $ 3 9 5 ( * 9 5 ( ) ' , 1 9 & & docid027739 rev 1 17/72 a6986f functional description 72 figure 5. soft-start phase the c ss is dimensioned accordingly with equation 1 : equation 1 where t ss is the soft-start time, i ss ch the charging current and v fb the reference of the error amplifier. the soft-start block supports the precharged output capacitor. t v cc v cch v ss inh v ss end t ss v ref ea reference ss/inh pin internal soft start signal v cc pin v ss start c ss ss ain i ssch t ss ? v fb ------------------------------- - ? 3 4 ? at ss ? 0.85v --------------------------- ? == functional description a6986f 18/72 docid027739 rev 1 figure 6. soft-start phase with precharged c out during normal operation a new soft-start cycle takes place in case of: ? thermal shutdown event ? uvlo event ? the device is driven in inh mode the soft-start capacitor is discharged with a 0. 6 ma typ. current cap ability for 1 msec time max. for complete and proper capacitor discharge in case of fault condition, a maximum c ss = 67 nf value is suggested. the application example in figure 7 shows how to enable the a6986f and perform the soft- start phase driven by an external voltage st ep, for example the signal from the ignition switch in automoti ve applications. figure 7. enable the device with external voltage step r up r dwn c ss ss/inh i ss ch v step ignition switch 1 p a typ in inhibit 4 p atypin ss i ss disch uvlo thermal shutdown = 600 p atyp docid027739 rev 1 19/72 a6986f functional description 72 the maximum capacitor value has to be limited to guarantee the device can discharge it in case of thermal shutdown and uvlo events (see figure 9 ), so restart the switching activity ramping the error amplif ier reference voltage. equation 2 where: equation 3 the optional diode prevents to disable the device if the external source drops to ground. r up value is selected in order to make the capacitor charge at first approximation independent from the internal current generator (4 ? a typ. current capability, see table 5 on page 8 ), so: equation 4 where: equation 5 represents the ss/inh voltage correspondent to the end of the ramp on the error amplifier (see figure 5 ); refer to table 5 for v ss start , v fb and ss gain parameters. as a consequence the voltage across the soft-start capacitor can be written as: equation 6 r ss_down is selected to guarantee the device stays in inhibit mode when the internal generator sources 1 ? a typ. out of the ss/inh pin and v step is not present: equation 7 so: equation 8 c ss 1 msec ? r ss_eq 1 v ss_final 0.9 v ? 600 ? ar ss_eq ? --------------------------------------------- - ? ?? ?? ln ? ------------------------------------------------------------------------------------------- ? r ss_eq r up r dwn ? r up r dwn + -------------------------------- - = v ss_final v step v diode ? ?? r dwn r up r dwn + --------------------------------- - ? = v step v diode ? v ss end ? r up ----------------------------------------------------------------------- i ss charge 4 ? a ? ? v ss end v ss start v fb ss gain -------------------- - + = v ss t ?? v ss_final 1 1e t c ss r ss_eq ? --------------------------------- ? ? ----------------------------------------- - ? = r dwn i ss inhibit r dwn 1 ? a ? v inh 200 mv ? ? ? ? r dwn 100 k ? ? functional description a6986f 20/72 docid027739 rev 1 r up and r dwn are selected to guarantee: equation 9 the time to ramp the internal voltage reference can be calculated from equation 10 : equation 10 that is the equivalent soft-start time to ramp the output voltage. figure 8 shows the soft-start phase with the following component selection: r up = 180 k ? , r dwn = 33 k ? , c ss = 200 nf, the 1n4148 is a small signal diode and v step = 13 v. figure 8. external soft-start network v step driven the circuit in figure 7 introduces a time delay between v step and the switching activity that can be calculated as: equation 11 figure 9 shows how the device discharges the soft-start capacitor after an uvlo or thermal shutdown event in order to restart the switching activity ramping the error amplifier reference voltage. v ss_final 2 v v ss_end ? ? ? v ss_final v ss end ? ---------------------------------------------------------- - ?? ?? ln ?? = t ss delay c ss r ss_eq v ss_final v ss_final v ss start ? ---------------------------------------------------------- - ?? ?? ln ?? = docid027739 rev 1 21/72 a6986f functional description 72 figure 9. external soft-start after uvlo or thermal shutdown functional description a6986f 22/72 docid027739 rev 1 5.3.1 ratiometric startup the ratiometric startup is implemented sharing t he same soft-start capacitor for a set of the a6986f devices. figure 10. ratiometric startup as a consequence all the internal current generators charge in parallel the external capacitor. the capacitor value is dimensioned accordingly with equation 12 : equation 12 where n a6986 represents the number of devices connected in parallel. for better tracking of the different output voltages the synchronization of the set of regulators is suggested. 9 2 8 7 9 2 8 7 9 2 8 7 w 9 $ 0 c ss n a6986 ss gain i ssch t ? ss v fb ------------------------------- - ? ? n a6986 3 4 ? at ss ? 0.85v --------------------------- ? ? == docid027739 rev 1 23/72 a6986f functional description 72 figure 11. ratiometric startup operation functional description a6986f 24/72 docid027739 rev 1 5.3.2 output voltage sequencing the a6986f device implements sequencing connecting the rst pin of the master device to the ss/inh of the slave. the slave is inhibited as long as the master output voltage is outside regulation so implementing the sequencing (see figure 12 ). figure 12. output voltage sequencing high flexibility is achieved thanks to the programmable rst thresholds ( table 7 on page 11 and table 8 on page 12 ) and programmable delay time. to minimize the component count the delay pin capacitor can be also omitted so the pin works as a normal power good. 5.4 error amplifier the voltage error amplifier is the core of the loop regulation. it is a transconductance operational amplifier whose no n inverting input is connected to the internal voltage reference (0.85 v), while the inverting input (fb) is connected to the external divider or directly to the output voltage. the error amplifier output is compared with the inductor current sense information to perform pwm control. the error amplifier also determines the burst operation at light-load when the lcm is active. 9 2 8 7 9 2 8 7 9 2 8 7 w 9 w ' ( / $ < w ' ( / $ < w ' ( / $ < $ 0 table 10. uncompensated error amplifier characteristics description values transconductance 155 s low frequency gain 100 db docid027739 rev 1 25/72 a6986f functional description 72 5.5 light-load operation the mlf pinstrapping during the power-up phase determines the light-load operation (refer to table 7 on page 11 and table 8 on page 12 ). 5.5.1 low noise mode (lnm) the low noise mode implements a forced pwm operation over the different loading conditions. the lnm features a constant switching frequency to minimize the noise in the final application and a constant voltage ripple at fixed v in . the regulator in steady loading condition never skip pulses and it operates in continuous conduction mode (ccm) over the different loading conditions. figure 13. low noise mode operation typical applications for the lnm operation are car audio and sensors. 5.5.2 low consumption mode (lcm) the low consumption mode maximizes the effici ency at light-load. the regulator prevents the switching activity whenev er the switch peak current request is lower than the i skip threshold. as a consequence the a6986f devi ce works in bursts and it minimizes the quiescent current request in the meantime between the switching operation. in lcm operation, the pin synch/iski p level dynamically defines the i skip current threshold (see table 5 on page 8 ) as shown in table 11 . functional description a6986f 26/72 docid027739 rev 1 the iskip programmab ility helps to optimize the performanc e in terms of the output voltage ripple or efficiency at the light-load, that are parameters which disagree each other by definition. a lower skip current level mini mizes the voltage ripple but incr eases the switching activity (time between bursts gets closer) since less energy per burst is transfered to the output voltage at the given load. on t he other side, a higher skip level reduces the switching activity and improves the efficiency at the light-load but worsen the voltage ripple. no difference in terms of the voltage ripple and conversion efficiency for the medium and high load current level, that is when the device operates in the discontinuous or continuous mode (dcm vs. ccm). figure 14 and figure 15 report the efficiency measurements to highlight the iskip h and iskip l efficiency gap at the light-load also in comparison with the lnm operation (also called noskip). the same efficiency at the medium / high load is confirmed at different iskip levels. figure 14. light-load efficiency comparison at different i skip - linear scale figure 15. light-load efficien cy comparison at different i skip - log scale table 11. i skip programmable current threshold synch / iskip (pin 4) i skip current threshold low iskip h = 0.4 a typical high iskip l = 0.2 a typical 60 65 70 75 80 85 90 95 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 a6986f vin=13.5 vout=5v vbias iskipl a6986f vin=13.5 vout=5v novbias iskipl a6986f vin=13.5 vout=5v novbias iskiph a6986f vin=13.5 vout=5v vbias iskiph a6986f vin=13.5 vout=5v novbias noskip a6986f vin=13.5 vout=5v vbias noskip lnm lcm iskiph =200ma lcm iskiph =400ma 30 40 50 60 70 80 90 0.001 0.01 0.1 a6986f vin=13.5 vout=5v vbias iskipl a6986f vin=13.5 vout=5v novbias iskipl a6986f vin=13.5 vout=5v novbias iskiph a6986f vin=13.5 vout=5v vbias iskiph a6986f vin=13.5 vout=5v novbias noskip a6986f vin=13.5 vout=5v vbias noskip lnm lcm ikiph =200ma lcm ikiph =400ma docid027739 rev 1 27/72 a6986f functional description 72 figure 16 and figure 17 show the lcm operation at the different iskip level. figure 16 shows the iskip h = 400 ma typ. and so 20 mv output voltage ripple. figure 17 shows the iskip l = 200 ma typ. and so 10 mv output voltage ripple. figure 16. lcm operation with iskip h = 400 ma typ. at zero load figure 17. lcm operation with iskip h = 200 ma typ. at zero load functional description a6986f 28/72 docid027739 rev 1 the lcm operation satisfies the requirements of the unswitched car body applications (kl30). these applications are directly connected to the battery and are operating when the engine is disabled. the typical load when t he car is parked is represented by a can transceiver and a microcontroller in sleep mode (total load is around 20 - 30 a). as soon as the transceiver recognizes a valid word in the bus, it awakes the c and the rest of the application. the typical input current request of the module when the car is parked is 100 a typ. to prevent the battery discharge over the parking time. in order to minimize the regulator quiescent current re quest from the input voltage, the v bias pin can be connected to an external voltage source in the range 3 v < v bias < 5.5 v (see section 5.1: power supply and voltage reference on page 15 ). in case the v bias pin is connected to the regulated output voltage (vout), the total current drawn from the input voltage can be calculated as equation 14 . given the energy stored in the inductor during a burst, the voltage ripple depends on the capacitor value: equation 13 figure 18. lcm operation over loading condition (part 1) v out ripple ? q il c out ------------- - i l t ?? dt ? ?? 0 t burst ? c out ------------------------------------------- - == docid027739 rev 1 29/72 a6986f functional description 72 figure 19. lcm operation over loading condition (part 2 - dcm) figure 20. lcm operation over loading condition (part 3 - dcm) functional description a6986f 30/72 docid027739 rev 1 figure 21. lcm operation over loading condition (part 4 - dcm) figure 22. lcm operation over loading condition (part 5 - ccm) docid027739 rev 1 31/72 a6986f functional description 72 5.6 switchover feature the switchover maximizes the efficiency at the light-load that is cruc ial for lcm applications. 5.6.1 lcm the lcm operation satisfies the high efficiency requirements of the battery powered applications. in order to minimize the regula tor quiescent current request from the input voltage, the v bias pin can be connected to an external voltage source in the range 3 v < v bias < 5.5 v (see section 5.1: power supply and voltage reference on page 15 ). in case the v bias pin is connected to the regulated output voltage (v out ), the total current drawn from the input voltage can be calculated as: equation 14 where iq op v in , iq op v bias are defined in table 5: electrical characteristics on page 8 and ? a6986 is the efficiency of the conversion in the working point. 5.6.2 lnm equation 14 is also valid when the device works in lnm and it can increase the efficiency at the medium load since the regulator always operates in the continuous conduction mode. 5.7 overcurrent protection the current protection circuitry features a cons tant current protection, so the device limits the maximum peak current (see table 5 ) in overcurrent condition. the a6986f device implements a pulse by pulse current sensing on both power elements (high-side and low-side switches) for effective current prot ection over the duty cycle range. the high-side current sensing is called ?peak? the low-side sensing ?valley?. the internal noise generated during the swit ching activity makes the current sensing circuitry ineffective for a mini mum conduction time of the power element. this time is called ?masking time? because the information from th e analog circuitry is masked by the logic to prevent an erroneous detection of the overcurrent event. as a consequence, the peak current protection is disabled for a masking ti me after the high-side switch is turned on, the valley for a masking time after the low-side swit ch is turned on. in other words, the peak current protection can be ineffective at ex tremely low duty cycle s, the valley current protection at extremely high duty cycles. the a6986f device assures an effective overcu rrent protection sensing the current flowing in both power elements. in case one of the two current sensing circuitry is ineffective because of the masking time, the device is pr otected sensing the current on the opposite switch. thus, the combination of the ?peak? and ?valley? current limits assure the effectiveness of the overcurr ent protection even in extr eme duty cycle conditions. the valley current threshold is designed higher than the peak to guarantee a proper operation. in case the current diverges becau se of the high-side masking time, the low-side power element is turned on until the switch current level drops below the valley current i qvin i qopvin 1 ? a6986 ----------------- v bias v in --------------- i qopvbias ? ? + = functional description a6986f 32/72 docid027739 rev 1 sense threshold. the low-side operation is able to prevent the high-side turn on, so the device can skip pulses decrea sing the swathing frequency. figure 23. valley current sense operation in overcurrent condition figure 23 shows the switching frequency reduction during the valley current sense operation in case of extremely low duty cycle (v in 38 v, f sw = 500 khz short-circuit condition). in a worst case scenario (like figure 23 ) of the overcurrent protection the switch current is limited to: equation 15 where i valley_th is the current threshold of the valley sensing circuitry (see table 5: electrical characteristics on page 8 ) and t mask_hs is the masking time of the high-side switch 100 nsec. typ.). in most of the overcurrent conditions the conduc tion time of the high-side switch is higher than the masking time and so the peak cu rrent protection limits the switch current. equation 16 i max = i peak_th i max i valleyth v in v out ? l ----------------------------- - t maskhs ? + = docid027739 rev 1 33/72 a6986f functional description 72 figure 24. peak current sense operation in overcurrent condition the dc current flowing in the load in overcurrent condition is: equation 17 ocp and switchover feature output capacitor discharging the current flowing to ground during heavy short-circuit events is only limited by parasitic elements like the output capacitor esr and short-circuit impedance. due to parasitic inductance of the short-circuit impedance, negative output voltage oscillations can be generated with hu ge discharging current levels (see figure 25 ). i dcoc v out ?? i max i ripple v out ?? 2 --------------------------------------- - ? i max v in v out ? 2l ? ----------------------------- - t on ? ?? ?? ? == functional description a6986f 34/72 docid027739 rev 1 figure 25. output voltage oscillations during heavy short-circuit figure 26. zoomed waveform the v bias pin absolute maximum ratings (see table 2: absolute maximum ratings on page 6 ) must be satisfied over the different dynamic conditions. if the v bias is connected to gnd there are no issues (see figure 25 and figure 26 ). short-circuit current regulated output voltage inductor current switching node regulated output voltage inductor current short-circuit current switching node short-circuit current regulated output voltage inductor current switching node regulated output voltage inductor current short-circuit current switching node docid027739 rev 1 35/72 a6986f functional description 72 a small resistor value (few ohms) in series with the v bias can help to limit the pin negative voltage (see figure 27 ) during heavy short-circuit events if it is connected to the regulated output voltage. figure 27. v bias in heavy short-circuit event 5.8 overvoltage protection the overvoltage protection monitors the fb pin and enables the low-side mosfet to discharge the output capacitor if the out put voltage is 20% over the nominal value. this is a second level protection and sh ould never be triggered in normal operating conditions if the system is properly dimens ioned. in other words, the selection of the external power components and the dynamic pe rformance determined by the compensation network should guarantee an output voltage regulation within the overvoltage threshold even during the worst case scenario in term of load transitions. the protection is reliable and also able to op erate even during normal load transitions for a system whose dynamic performance is not in line with the load dynamic request. as a consequence the output voltage regulation would be affected. figure 28 shows the overvoltage operation during a negative steep load transient for a system designed with huge inductor value and sm all output capacitor. the inductor value limits the switch current slew rate and the extr a charge flowing into th e small capacitor value generates an overvoltage event. this can be considered as an example for a system with dynamic performance not in line with the load request. the a6986f device implements a 1 a typ. ne gative current limitation to limit the maximum reversed switch current during the overvoltage operation. v bias pin voltage regulated output voltage inductor current switching node (purple) (cyan) regulated output voltage vbias pin short-circuit current switching node functional description a6986f 36/72 docid027739 rev 1 figure 28. overvoltage operation 5.9 thermal shutdown the shutdown block disables the switching activity if the junction temperature is higher than a fixed internal threshold (165 c typical). the thermal sensing element is close to the power elements, ensuring fast and accurate temperature detection . a hysteresis of approximately 30 c prevents the device from turning on and off continuously. when the thermal protection runs away a new soft-start cycle will take place. docid027739 rev 1 37/72 a6986f closing the loop 72 6 closing the loop figure 29. block diagram of the loop 6.1 g co (s) control to output transfer function the accurate control to output transfer function for a buck peak current mode converter can be written as: equation 18 where r load represents the load resistance, r i the equivalent sensing resistor of the current sense circuitry, ? ? p the single pole introduced by the the power stage and ? z the zero given by the esr of the output capacitor. f h (s) accounts the sampling effect performed by the pwm comparator on the output of the error amplifier that introduces a double pole at one half of the switching frequency. 9 , 1 5 h v l v w r u g l y l g h u / & i l o w h u 9 5 ( ) ( u u r u d p s o l i l h u ) % & r p s h q v d w l r q q h w z r u n 3 : 0 f r p s d u d w r u + 6 v z l w f k 5 5 / & 2 8 7 & 3 5 & & & 3 : 0 f r q w u r o & x u u h q w v h q v h / 6 v z l w f k , + 6 j & 6 5 / 2 $ ' $ 0 g co s ?? r load g cs 1 1 r load t sw ? l ----------------------------------- m c 1d ? ?? ? 0.5 ? ?? ? + ------------------------------------------------------------------------------------------------------- - ? 1 s ? z ------ + ?? ?? 1 s ? p ------ + ?? ?? --------------------- - f h ? s ?? ? ? = closing the loop a6986f 38/72 docid027739 rev 1 equation 19 equation 20 where: equation 21 s n represents the on time slope of the sensed inductor current, s e the on time slope of the external ramp (v pp peak-to-peak amplitude) that im plements the slope compensation to avoid sub-harmonic oscillation s at duty cycle over 50%. s e can be calculated from the parameter v pp ?? g cs given in table 5 on page 8 . the sampling effect contribution f h (s) is: equation 22 where: equation 23 ? z 1 esr c out ? --------------------------------- = ? p 1 r load c out ? -------------------------------------- - m c 1d ? ?? ? 0.5 ? lc out f sw ? ? ---------------------------------------------- + = m c 1 s e s n ------ + = s e v pp g cs f sw ?? = s n v in v out ? l ---------------------------- - = ? ? ? ? ? ? ? ? f h s ?? 1 1 s ? n q p ? ------------------- - s 2 ? n 2 --------- ++ ---------------------------------------------- = q p 1 ? m c 1d ? ?? 0.5 ? ? ?? ? ----------------------------------------------------------- - = docid027739 rev 1 39/72 a6986f closing the loop 72 6.2 error amplifier compensation network the typical compensation network require d to stabilize the system is shown in figure 30 . figure 30. transconductance embedded error amplifier r c and c c introduce a pole and a zero in the open loop gain. c p does not significantly affect system stability but it is useful to reduce th e noise at the output of the error amplifier. the transfer function of the error amplifier and its compensation network is: equation 24 where a vo = g m r o the poles of this transfer function are (if c c >> c 0 + c p ): equation 25 & 3 5 & & & ) % & 2 0 3 g 9 5 * p g 9 9 ( $ 5 & & & & 3 & 9 5 ( ) 9 $ 0 a 0 s ?? a v0 1sr c c c ? ? + ?? ? s 2 r 0 c 0 c p + ?? ? r c c c sr 0 c c r 0 c 0 c p + ?? ? + ? r c c c ? + ?? 1 + ? + ? ? ? ------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------- = f plf 1 2 ? r 0 c c ? ? ? ------------------------------------- = closing the loop a6986f 40/72 docid027739 rev 1 equation 26 whereas the zero is defined as: equation 27 6.3 voltage divider the contribution of the internal voltage di vider for fixed output voltage devices is: equation 28 while adjustable output part number is: equation 29 a small signal capacitor in para llel to the upper resistor (see figure 31 ) of the voltage divider implements a leading network (f zero < f pole ), sometimes necessary to improve the system phase margin: figure 31. leading network example f phf 1 2 ? r 0 c 0 c p + ?? ? ? ? -------------------------------------------------------- = f z 1 2 ? r c c c ? ? ? ------------------------------------- = g div s ?? r 2 r 1 r 2 + -------------------- v fb v out -------------- 0.85 3.3 ----------- 0.2575 = a6986f3v 0.85 5 ----------- 0.17 = a6986f5v === g div s ?? r 2 r 1 r 2 + -------------------- = v l j q d o * 1 ' 3 : 5 j q g 3 : 5 j q g 9 2 8 7 $ 9 % , $ 6 5 6 7 9 & & 6 6 , 1 + 6 < 1 & + ) 6 : 0 / ) & 2 0 3 ' ( / $ < ) % 6 * 1 ' 3 * 1 ' 3 * 1 ' / ; / ; 9 , 1 ( 3 5 & s * 1 ' * 1 ' & u 5 & f 9 , 1 5 f $ 0 9 a6986f docid027739 rev 1 41/72 a6986f closing the loop 72 laplace transformer of the leading network: where: equation 30 6.4 total loop gain in summary, the open loop gain can be expressed as: equation 31 example 1 v in = 12 v, v out = 3.3 v, r out = 2.2 ? selecting f sw = 500khz, l = 6.8 h, c out = 20f and esr = 1 m ? , r c = 75 k ? , c c = 220 pf, c p = 2.2 pf (please refer to table 17 on page 56 ), the gain and phase bode diagrams are plotted respectively in figure 32 and figure 33 . g div s ?? r 2 r 1 r 2 + -------------------- 1sr 1 c r1 ? ++ ?? 1s r 1 r 2 ? r 1 r 2 + -------------------- ? c r1 ? + ?? ?? ------------------------------------------------------------- ? = f z 1 2 ? r 1 c r1 ? ? ? ----------------------------------------- = f p 1 2 ? r 1 r ? 2 r 1 r 2 + -------------------- c r1 ? ? ? ------------------------------------------------------- = f z f p ? ?? g div s ?? g co s ?? a 0 s ?? ?? = closing the loop a6986f 42/72 docid027739 rev 1 figure 32. module plot equation 32 figure 33. phase plot the blue solid trace represents the transfer function including the sampling effect term (see equation 22 on page 38 ), the dotted blue trace neglects the contribution. x x x x x & 9 5 & 3 / " - - 0 0 1 . 0 % 6 - & ' s f r v f o d z < ) [ > . p e v m f < e # > bw 60khz = phase margin 70 0 = 0.1 1 10 100 110 3 u 110 4 u 110 5 u 110 6 u 110 7 u 0 22.5 45 67.5 90 112.5 135 157.5 180 external loop gain phase frequency [hz] phase docid027739 rev 1 43/72 a6986f closing the loop 72 6.5 compensation network design the maximum bandwidth of the system can be designed up to f sw /6 up to 150 khz maximum to guarantee a valid small signal model. equation 33 equation 34 where: equation 35 ? p is defined by equation 20 on page 38 , g cs represents the current sense transconductance (see table 5: electrical characteristics on page 8 ) and g m typ the error amplifier transconductance. equation 36 example 2 considering v in = 12 v, v out = 3.3 v, l = ? h, c out = 15 ? f, f sw = 500 khz, i out = 1 a. the maximum system bandwidth is 80 khz. assuming to design the compensation network to achieve a system bandwidth of 70 khz: equation 37 equation 38 so accordingly with equation 34 and equation 36 : equation 39 equation 40 the gain and phase bode diagrams are plotted respectively in figure 32 and figure 33 . bw f sw 6 -------- - = r c 2 ? bw c out v out ?? ? ? 0.85v g cs g m typ ?? --------------------------------------------------------------- - = f pole ? p 2 ? ? ---------- - = c c 5 2 ? r c bw ?? ? ------------------------------------- - = f pole 3.5khz = r load v out i out -------------- 3.3 ? == r c 68k ? = c c 165pf 180pf ? = closing the loop a6986f 44/72 docid027739 rev 1 figure 34. magnitude plot for example 2 figure 35. phase plot for example 2 0.1 1 10 100 110 3 u 110 4 u 110 5 u 110 6 u 110 7 u 30 17 4 9 22 35 48 61 74 87 100 external loop module frequency [hz] module [db] 0.1 1 10 100 110 3 u 110 4 u 110 5 u 110 6 u 110 7 u 0 22.5 45 67.5 90 112.5 135 157.5 180 external loop gain phase frequency [hz] phase docid027739 rev 1 45/72 a6986f application notes 72 7 application notes 7.1 output voltage adjustment the error amplifier reference voltage is 0.85 v typical. the output voltage is adjusted accordingly with equation 41 (see figure 36 ): equation 41 c r1 capacitor is sometimes useful to increase the small signal phase margin (please refer to section 6.5: compensation network design ). figure 36. a6986f application circuit 7.2 switching frequency a resistor connected to the fsw pin features the selection of the switching frequency. the pinstrapping is performed at power-up, before the soft-start takes place. the fsw pin is pinstrapped and then driven floating in order to minimize the quiescent current from vin. please refer to table 6: f sw selection on page 11 to identify the pull- up / pull-down resistor value. f sw = 250 khz / f sw = 500 khz preferred codifications don't require any external resistor. 7.3 mlf pin a resistor connected to the mlf pin features the selection of the between low noise mode / low consumption mode and the different rst thresholds. the pinstrapping is performed at power-up, before the soft-start takes place. the fsw pin is pinstrapped and then driven floating in order to minimize the quiescent cu rrent from vin. please refer to table 7 on page 11 , table 8 on page 12 , and table 9 on page 12 to identify the pull-up / pull-down resistor value. (lnm, rst threshold 93%) / (lcm, rst threshold 93%) preferred codifications don't require any external resistor. v out 0.85 1 r 1 r 2 ------ - + ?? ?? ? = signal gnd pwr gnd pwr gnd uc rst a6986f a6986f vbias rst vcc ss/inh synch fsw mlf comp delay fb sgnd pgnd pgnd lx lx vin ep 10uf 10uf vout vout 470nf 470nf gnd gnd 10nf 10nf 1uf 1uf gnd gnd 6.8uh 6.8uh 20uf 20uf 68nf 68nf 1m 1m rc rc vin vin cc cc application notes a6986f 46/72 docid027739 rev 1 7.4 voltage supervisor the embedded voltage supervisor (composed of the rst and the delay pins) monitors the regulated output voltage and keeps the rst open collector output in low impedance as long as the v out is out of regulation. in order to ensure a proper reset of digital devices with a valid power supply, the device can delay the rst assertion with a programmable time. figure 37. voltage supervisor operation the comparator monitoring the fb voltage has four different programmable thresholds (80%, 87%, 93%, 96% nominal output voltage) for high flexibility (see section 7.3: mlf pin on page 45 , table 7 on page 11 , table 8 on page 12 , and table 9 on page 12 ). when the rst comparator detects the output voltage is in regulation, a 2 ? a internal current source starts to charge an external capacitor to implement a voltage ramp on the delay pin. the rst open collector is then released as soon as v delay = 1.234 v (see figure 37 ). the cdelay is dimensioned accordingly with equation 42 : equation 42 the maximum suggested capacitor value is 270 nf. c delay i ssch t delay ? v delay ----------------------------------------- - 2 ? at delay ? 1.234v ------------------------------------- == docid027739 rev 1 47/72 a6986f application notes 72 7.5 synchronization (lnm) beating frequency noise is an issue when multiple switching regulators populate the same application board. the a6986f synchronization circuitry features the same switching frequency for a set of regulators simply conn ecting their synch pin together, so preventing beating noise. the master device provides the synchronization signal to the others since the synch pin is i/o able to deliver or recognize a frequency signal. for proper synchronization of multiple regulators, all of them have to be configured with the same switching frequency (see table 6 on page 11 ), so the same resistor connected at the fsw pin. in order to minimize the rms current flowing through the input filter, the a6986f device provides a phase shift of 180 between t he master and the sla ves. if more than two devices are synchronized, all slaves will have a common 180 phase shift with respect to the master. considering two synchronized a6986f which regulates the same output voltage (i.e.: operating with the same duty cycle), the input filter rms current is optimized and is calculated as: equation 43 the graphical representation of the input rms curr ent of the input filter in the case of two devices with 0 phase shift (synchronized to an external signal) or 180 phase shift (synchronized connecting their synch pins) re gulating the same output voltage is provided in figure 38 . to dimension the proper inpu t capacitor please refer to section 7.6.1: input capacitor selection on page 51 . figure 38. input rms current i rms i out 2 ----------- - 2d 1 2d ? ?? ? if d < 0.5 ? i out 2 ----------- - 2d 1 ? ?? 22d ? ?? ? if d > 0.5 ? ? ? ? ? ? ? ? = 5 0 6 f x u u h q w q r u p d o l ] h g , u p v , 2 8 7 w z r u h j x o d w r u v r s h u d w l q j l q s k d v h w z r u h j x o d w r u v r s h u d w l q j r x w r i s k d v h ' x w \ f \ f o h application notes a6986f 48/72 docid027739 rev 1 figure 39 shows two regulators not synchronized. figure 39. two regulators not synchronized figure 40 shows the same regulators working synchronized. the master regulator (lx2 trace) delivers the synchronization signal (synch1, synch2 pins are connected together) to the slave device (lx1). the slave regula tor works in phase with the synchronization signal which is out of phase wit h the master switching operation. figure 40. two regulators synchronized docid027739 rev 1 49/72 a6986f application notes 72 multiple a6986f can be synchronized to an exte rnal frequency signal fed to the synch pin. in this case the regulator set is phased to the re ference and all the devices will work with 0 phase shift. the frequency range of the synchronization signal is 275 khz - 2 mhz and the minimum pulse width is 100 nsec (see figure 41 ). figure 41. synchroniz ation pulse definition since the slope compensation contribution that is required to prevent subharmonic oscillations in peak current mo de architecture depends on t he switching freq uency, it is important to select the same oscillator frequency for all regula tors (all of them operate as slave) as close as possible to the frequency of the reference signal (please refer to table 6: f sw selection on page 11 ). as a consequence all the regulators have the same resistor value connected to the fsw pin, so the slope compensation is optimized accordingly with the frequency of the synchronization signal. the slope compensation contribution is latched at power-up and so fixed during the device operation. the a6986 normally operates in master mo de, driving the synch line at the selected oscillator frequency as shown in figure 42 and figure 39 . in slave mode the a6986 sets the intern al oscillator at 250 khz typ. (see table 6 on page 11 - first row) and drives the line accordingly. figure 42. a6986 synchronization driving capability in order to safely guarantee that each regulator recognizes itself in slave mode during the normal operation, the external master mu st drive the synch pin with a clock signal f synchro 100nsec min. 275khz < f synchro < 2mhz f synchro 100nsec min. v cc int 5 ma 0.7 ma f osc 150nsec typ. high level low level application notes a6986f 50/72 docid027739 rev 1 frequency higher than the maximu m oscillator spread (refer to table 6 on page 11 ) for at least 10 internal clock cycles. for example: selecting r fsw = 0 ?? to gnd the device enters in slave mode after 10 pulse s at frequency higher than 550 khz and so it is able to synchronize to a clock signal in the range 275 khz - 2 mhz (see figure 41 ). anyway it is suggested to limit the frequency range within 20% fsw resistor nominal frequency (see details in text be low). if not spread spectrum is required, all the regulators synchronize to a frequency higher to the maximum oscilla tor spread (550 khz in the example). the device keeps operating in slave mode as fa r as the master is able to drive the synch pin faster than 275 khz (maxim um oscillator spread for 250 khz oscillator), otherwise it goes back into master mode at the nominal oscilla tor frequency after succ essfully driving one pulse at 250 khz (see figure 43 ) in the synch line. figure 43. slave to master mode transition the external master can force a latched sla ve mode driving the synch pin low at power- up, before the soft-start starts the switching activity. so the oscillator frequency is 250 khz typ. fixed until a new uvlo event is triggered regardless fsw resistor value, that otherwise counts to design the slope compensation. t he same considerations above are also valid. table 12. example of oscillat or frequency selection from table 6 symbol r vcc (e24 series) r gnd (e24 series) f sw min. f sw typ. f sw max. f sw nc 0 ? 450 500 550 250khz typ. slave mode stand alone operation at nominal fsw synch signal switching node docid027739 rev 1 51/72 a6986f application notes 72 the master driving capability must be able to provide the prope r signal levels at the synch pin (see table 5 on page 8 - synchronization section): ? low level < v syn thl = 0.7 v sinking 5 ma ? high level > v syn thh = 1.2 v sourcing 0.7 ma figure 44. master driving capability to synchronize the a6986 as anticipated above, in slave mode the internal oscillator ope rates at 250 khz typ. but the slope compensation is dimensioned accordingly with fsw resistors so, even if the a6986f supports synchronization over the 275 khz - 2 mhz frequency range, it is important to limit the switching operation around a working po int close to the selected frequency (fsw resistor). as a consequence, to guarantee the full output curren t capability and to prevent the subharmonic oscillations the mast er must limit the driving fr equency range wit hin 20% of the selected frequency. a wider frequency range may generate subharmonic oscillati on for duty > 50% or limit the peak current capability (see i pk parameter in table 5 ) since the internal slope compensation signal may be saturated. 7.6 design of the power components 7.6.1 input capacitor selection the input capacitor voltage rating must be higher than the maximum input operating voltage of the application. during the switching activity a pulsed current flows into the input capacitor and so its rms current capability must be se lected accordingly with the application conditions. internal losses of the input filter depends on the esr value so usually low esr capacitors (like multilayer ce ramic capacitors) have higher rm s current capability. on the other hand, given the rms current value, lowe r esr input filter has lower losses and so contributes to higher conversion efficiency. the maximum rms input current flowing through the capacitor can be calculated as: r l r h v syn_th_h v syn_th_l v ccm 5 ma 0.7 ma application notes a6986f 52/72 docid027739 rev 1 equation 44 where i out is the maximum dc output current, d is the duty cycles, ? is the efficiency. this function has a maximum at d = 0.5 and, considering ? = 1, it is equal to io/2. in a specific application the range of possible duty cycles has to be considered in order to find out the maximum rms input current. th e maximum and minimum duty cycles can be calculated as: equation 45 equation 46 where ? v high_side and ? v low_side are the voltage drops across the embedded switches. the peak-to-peak voltage across the i nput filter can be calculated as: equation 47 in case of negligible esr (mlcc capacitor) the equation of cin as a function of the target vpp can be written as follows: equation 48 considering ?????? this function has its maximum in d = 0.5: equation 49 typically c in is dimensioned to keep the maximum peak-peak voltage across the input filter in the order of 5% v in_max . table 13. input capacitors manufacturer series size cap value ( ? f) rated voltage (v) tdk c3225x7s1h106m 1210 10 50 c3216x5r1h106m 1206 taiyo yuden umk325bj106mm-t 1210 i rms i out 1 d ? --- - ? ?? ?? d ? --- - ? ? = d max v out ? v lowside + v inmin ? v lowside ? v highside ? + ------------------------------------------------------------------------------------------------ = d min v out ? v lowside + v inmax ? v lowside ? v highside ? + ------------------------------------------------------------------------------------------------- - = v pp i out c in f sw ? ------------------------ - 1 d ? --- - ? ?? ?? d ? --- - ? ? esr i out ? i l + ?? ? + = c in i out v pp f sw ? ------------------------- - 1 d ? --- - ? ?? ?? d ? --- - ? ? = c inmin i out 4v ppmax f sw ? ? ---------------------------------------------- = docid027739 rev 1 53/72 a6986f application notes 72 7.6.2 inductor selection the inductor current ripple flowing into the ou tput capacitor determines the output voltage ripple (please refer to section 7.6.3 ). usually the inductor value is selected in order to keep the current ripple lower than 20% - 40% of the output current over the input voltage range. the inductance value can be calculated by equation 50 : equation 50 where t on and t off are the on and off time of the internal power switch. the maximum current ripple, at fixed v out, is obtained at maximum t off that is at minimum duty cycle (see section 7.6.1: input capacitor selection to calculate minimum duty). so fixing ? i l = 20% to 40% of the maximum output current, the minimum inductance value can be calculated: equation 51 where f sw is the switching frequency 1/(t on + t off ). for example for v out = 3.3 v, v in = 12 v, i o = 2 a and f sw = 500 khz the minimum inductance value to have ? i l = 30% of io is about 8.2 h. the peak current through the inductor is given by: equation 52 so if the inductor value decreases, the peak current (that has to be lower than the current limit of the device) increases. the higher is the inductor value, the higher is the average output current that can be delivered , without reaching the current limit. in table 14 some inductor part numbers are listed. 7.6.3 output capacitor selection the triangular shape current ripple (with zero average value) flowing into the output capacitor gives the output voltage ripple, that depends on the capacitor value and the equivalent resistive component (esr). as a consequence the output capacitor has to be selected in order to have a voltage ripple compliant with the application requirements. table 14. inductors manufacturer series inductor value ( ? h) saturation current (a) coilcraft xal50xx 2.2 to 22 6.5 to 2.7 xal60xx 2.2 to 22 12.5 to 4 ? i l v in v out ? l ----------------------------- - t on ? v out l -------------- t off ? == l min v out ? i lmax ------------------- 1d min ? f sw ---------------------- - ? = i lpk ? i out ? i l 2 -------- + = application notes a6986f 54/72 docid027739 rev 1 the voltage ripple equation can be calculated as: equation 53 usually the resistive component of the ripple can be neglected if the selected output capacitor is a multi layer ceramic capacitor (mlcc). the output capacitor is important also for loop stability: it determines the main pole and the zero due to its esr. (see section 6: closing the loop on page 37 to consider its effect in the system stability). for example with v out = 3.3 v, v in = 12 v, ? i l = 0.6 a, f sw = 500 khz (resulting by the inductor value) and c out = 10 ? f mlcc: equation 54 the output capacitor value has a key role to sustain the output voltage during a steep load transient. when the load transient slew ra te exceeds the system bandwidth, the output capacitor provides the current to the load. in case the final application specifies high slew rate load transient, th e system bandwidth must be maximi zed and the output capacitor has to sustain the output volta ge for time response shorter than the loop response time. in table 15 some capacitor series are listed. table 15. output capacitors manufacturer series cap value ( ? f) rated voltage (v) esr (m ? ) murata grm32 22 to 100 6.3 to 25 < 5 grm31 10 to 47 6.3 to 25 < 5 panasonic ecj 10 to 22 6.3 < 5 eefcd 10 to 68 6.3 15 to 55 sanyo tpa/b/c 100 to 470 4 to 16 40 to 80 tdk c3225 22 to 100 6.3 < 5 ? v out esr ? ? i lmax ? i lmax 8c out f sw ? ? --------------------------------------- + = ? v out v out ------------------ 1 v out -------------- ? i lmax c out f sw ? ------------------------------ ? ? 1 33 ------ 06 ? 810 ? f 500khz ? ? -------------------------------------------------- ? ?? ?? 15mv 3.3 --------------- - 0.45% === docid027739 rev 1 55/72 a6986f application board 72 8 application board the reference evaluation bo ard schematic is shown in figure 45 . figure 45. evaluation board schematic the additional input filter (c16, l3, c15, l2, c14) limits the conducted emission on the power supply (refer to section 10 on page 63 ). signal gnd power gnd 10v vin_flt pgnd vin_flt pgnd c14 4.7uf c14 4.7uf + c13a nm + c13a nm j5 j5 r4 0 r4 0 r11 10r r11 10r tp3 synch tp3 synch c8 bom c8 bom j3 j3 l1 6.8uh l1 6.8uh tp8 vin_emi tp8 vin_emi c9 10uf c9 10uf r10 nm r10 nm c2 100nf 50v c2 100nf 50v + c13 bom + c13 bom c6 10nf c6 10nf r2 nm r2 nm c16 4.7uf c16 4.7uf c4 2.2p c4 2.2p r6 1m r6 1m c10 10 uf c10 10 uf tp7 gnd tp7 gnd j2 j2 tp2 rst tp2 rst r3 nm r3 nm r9 nm r9 nm tp1 ss/inh tp1 ss/inh c11 nm c11 nm c1 bom c1 bom r5 nm r5 nm r7 0r r7 0r r1 0 r1 0 c15 4.7uf c15 4.7uf c7 nm c7 nm j1 j1 tp6 gnd tp6 gnd u1 a6986f u1 a6986f rst 1 vcc 2 ss/inh 3 synch 4 fsw 5 mlf 6 comp 7 delay 8 fb 9 sgnd 10 pgnd 11 pgnd 12 lx 13 lx 14 vin 15 vbias 16 ep 17 j4 j4 tp4 vout tp4 vout l3 mpz2012s221a l3 mpz2012s221a c5 68nf c5 68nf l2 4.7uh l2 4.7uh c3 470nf c3 470nf r8 bom r8 bom tp5 vin tp5 vin table 16. bill of material (communal parts) reference part number description manufacturer c1, c9, c10 cga5l3x5r1h106k 10 ? f - 1206 - 50 v - x5r - 10% tdk c2 c2012x7s2a105k 1 ? f - 0805 - 50 v - x7s - 10% tdk c3 470 nf - 50 v - 0603 c4, c7, c8 see table 17 / table 18 / table 19 c5 68 nf - 50 v - 0603 c6 10 nf - 50 v - 0603 c14, c15, c16 c3216x7r1h475k 4.7 ? f - 1206 - 50 v - x7r - 10% tdk c11, c13, c13a not mounted r1, r4 0 ? - 0603 r6 1 m ? - 1%- 0603 r7, r8, r9 see table 17 / table 18 / table 19 r11 10 ? - 1% - 0603 r2, r3, r5, r10 not mounted application board a6986f 56/72 docid027739 rev 1 l1 xal5050-682mec 6.8 ? hcoilcraft l2 xal4030-472mec 4.7 ? hcoilcraft l3 mpz2012s221a emc bead tdk j1 open j2 open j3 see table 17 / table 18 / table 19 j4 open j5 to adjust the iskip current level in lcm operation. leave open in lnm u1 a6986f 3v3 3.3 v internal divider stm table 16. bill of material (communal parts) (continued) reference part number description manufacturer table 17. a6986f 3v3 demonstration board bom reference part number description manufacturer r7 0 r - 0603 r9, c7 not mounted r8 75 k ? - 1% - 0603 c8 220 pf - 50 v - 0603 c4 2.2 pf - 50 v - 0603 j3 closed switchover enabled l1 xal4030-682mec 6.8 ? hcoilcraft u1 a6986f 3v3 3.3 v internal divider stm table 18. a6986f 5v demonstration board bom reference part number description manufacturer r7 0 r - 0603 r9, c7 not mounted r7 0 ? - 0603 r8 110 k ? - 1% - 0603 c8 150 pf - 50 v - 0603 c4 2.2 pf - 50 v - 0603 j3 closed switchover enabled l1 xal4030-682mec 6.8 ? hcoilcraft u1 a6986f 5v 5 v internal divider stm docid027739 rev 1 57/72 a6986f application board 72 table 19. a6986f adj. demonstration board bom for table 17 bode?s plot please refer to section 6.4 on page 41 . figure 46 and figure 47 show the magnitude and phase margin bode?s plots related to table 18 . the small signal dynamic performance in this configuration is: equation 55 figure 46. magnitude bode?s plot reference part number description manufacturer r7 200 k ? - 1% - 0603 c7 3.3 pf - 50 v - 0603 r9 33 k ? - 1% - 0603 r8 180 k ? - 1% - 0603 c8 62 pf - 50 v - 0603 c4 2.2 pf - 50 v - 0603 j3 open switchover enabled l1 xal4040-103mec 10 ? hcoilcraft u1 a6986f external divider stm bw 57khz = phase margin 70 0 = 0.1 1 10 100 110 3 u 110 4 u 110 5 u 110 6 u 110 7 u 30 17 4 9 22 35 48 61 74 87 100 external loop module f[h] module [db] application board a6986f 58/72 docid027739 rev 1 figure 47. phase margin bode?s plot 0.1 1 10 100 110 3 u 110 4 u 110 5 u 110 6 u 110 7 u 0 22.5 45 67.5 90 112.5 135 157.5 180 external loop gain phase frequency [hz] phase docid027739 rev 1 59/72 a6986f application board 72 figure 48. top layer figure 49. bottom layer efficiency curves a6986f 60/72 docid027739 rev 1 9 efficiency curves figure 50. efficiency: v in = 13.5 v - v out = 3.3 v - fsw = 500 khz figure 51. efficiency curves: v in = 13.5 v - v out = 3.3 v - fsw = 500 khz (log scale) figure 52. efficiency curves: v in = 13.5 v - v out = 5 v - fsw = 500 khz $ ) 9 , 1 9 2 8 7 9 9 % , $ 6 , 6 . , 3 / $ ) 9 , 1 9 2 8 7 9 1 2 9 % , $ 6 , 6 . , 3 / $ ) 9 , 1 9 2 8 7 9 1 2 9 % , $ 6 , 6 . , 3 + $ ) 9 , 1 9 2 8 7 9 9 % , $ 6 , 6 . , 3 + $ ) 9 , 1 9 2 8 7 9 9 % , $ 6 1 2 6 . , 3 $ ) 9 , 1 9 2 8 7 9 1 2 9 % , $ 6 1 2 6 . , 3 20 30 40 50 60 70 80 0.001 0.01 0.1 a6986f vin=13.5 vout=3v3 vbias iskipl a6986f vin=13.5 vout=3v3 novbias iskipl a6986f vin=13.5 vout=3v3 novbias iskiph a6986f vin=13.5 vout=3v3 vbias iskiph a6986f vin=13.5 vout=3v3 vbias noskip a6986f vin=13.5 vout=3v3 novbias noskip 60 65 70 75 80 85 90 95 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 a6986f vin=13.5 vout=5v vbias iskipl a6986f vin=13.5 vout=5v novbias iskipl a6986f vin=13.5 vout=5v novbias iskiph a6986f vin=13.5 vout=5v vbias iskiph a6986f vin=13.5 vout=5v novbias noskip a6986f vin=13.5 vout=5v vbias noskip docid027739 rev 1 61/72 a6986f efficiency curves 72 figure 53. efficiency curves: v in = 13.5 v - v out = 5 v - fsw = 500 khz (log scale) figure 54. efficiency curves: v in = 24 v - v out = 3.3 v - fsw = 500 khz figure 55. efficiency curves: v in = 24 v - v out = 3.3 v - fsw = 500 khz (log scale) 30 40 50 60 70 80 90 0.001 0.01 0.1 a6986f vin=13.5 vout=5v vbias iskipl a6986f vin=13.5 vout=5v novbias iskipl a6986f vin=13.5 vout=5v novbias iskiph a6986f vin=13.5 vout=5v vbias iskiph a6986f vin=13.5 vout=5v novbias noskip a6986f vin=13.5 vout=5v vbias noskip 45 50 55 60 65 70 75 80 85 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 a6986f vin=24 vout=3v3 vbias iskipl a6986f vin=24 vout=3v3 novbias iskipl a6986f vin=24 vout=3v3 novbias iskiph a6986f vin=24 vout=3v3 vbias iskiph a6986f vin=24 vout=3v3 vbias noskip a6986f vin=24 vout=3v3 novbias noskip 20 30 40 50 60 70 80 0.001 0.01 0.1 a6986f vin=24 vout=3v3 vbias iskipl a6986f vin=24 vout=3v3 novbias iskipl a6986f vin=24 vout=3v3 novbias iskiph a6986f vin=24 vout=3v3 vbias iskiph a6986f vin=24 vout=3v3 vbias noskip a6986f vin=24 vout=3v3 novbias noskip efficiency curves a6986f 62/72 docid027739 rev 1 figure 56. efficiency curves: v in = 24 v - v out = 5 v - fsw = 500 khz figure 57. efficiency curves: v in = 24 v - v out = 5 v - fsw = 500 khz (log scale) $ ) 9 , 1 9 2 8 7 9 9 % , $ 6 , 6 . , 3 / $ ) 9 , 1 9 2 8 7 9 1 2 9 % , $ 6 , 6 . , 3 / $ ) 9 , 1 9 2 8 7 9 1 2 9 % , $ 6 , 6 . , 3 + $ ) 9 , 1 9 2 8 7 9 9 % , $ 6 , 6 . , 3 + $ ) 9 , 1 9 2 8 7 9 1 2 9 % , $ 6 1 2 6 . , 3 $ ) 9 , 1 9 2 8 7 9 9 % , $ 6 1 2 6 . , 3 20 30 40 50 60 70 80 0.001 0.01 0.1 a6986f vin=24 vout=5v vbias iskipl a6986f vin=24 vout=5v novbias iskipl a6986f vin=24 vout=5v novbias iskiph a6986f vin=24 vout=5v vbias iskiph a6986f vin24 vout=5v novbias noskip a6986f vin=24 vout=5v vbias noskip docid027739 rev 1 63/72 a6986f emc testing results 72 10 emc testing results this section reports emc testing results for the a6986f evaluation board (see section 8 on page 55 ) accordingly with the following test methods: ? ce 150r for conducted emission ? dp for conducted immunity all the measurement were performed at i load = 10% and 80% as defined in table 22 . dpi: 30 dbm for global pins, 12 dbm for local pins. all the pins under dpi testing (see table 22 ) satisfy class 3 limits.. table 20. ce 150r test method conducted emission, ce 150r frequency range 150 khz - 30 mhz 30 mhz - 1 ghz bandwidth 9 khz 120 khz step size 5 khz 60 khz dwell time 2 complete so ftware cycles minimum detectors peak + average table 21. dpi test method conducted immunity, dpi frequency range 10 khz - 150 khz 150 khz - 1 mhz 1 mhz - 10 mhz 10 mhz - 100 mhz 100 mhz - 200 mhz 200 mhz - 400 mhz 400 mhz - 1 ghz step size (linear) 10 khz 100 khz 500 khz 1 mhz 2 mhz 4 mhz 10 mhz dwell time 2 sec. but min. 2 software complete cycles modulation cw am 1 khz, 80% (same peak value as cw) table 22. pin testing pin name remarks classification ce dpi vs1 filtered vin pin global x x vin vin pin global x x vout regulated output voltage local x rst rst pin local x ss/inh ss/inh pin local x (x) emc testing results a6986f 64/72 docid027739 rev 1 figure 58 shows the schematic of the emc board that can be configured for ce and dpi testing. figure 58. ce - 150r / dpi signal gnd power gnd a6986f - 500khz - ce version 2a dc 2a dc 2a dc 50ohm 50ohm 50ohm 50ohm 50ohm 50ohm 50ohm ce 150ohm assembly version: rf networks: mount 120r mount 6.8nf mount 51r dpi assembly version: rf networks: change 120r into 0r mount 6.8nf don't mount 51r gnd-rf gnd-rf vs1 gnd-rf gnd-rf vs2 gnd-rf gnd-rf vin_pin gnd-rf gnd-rf vout gnd-rf gnd-rf rst gnd-rf gnd-rf ss_inh gnd-rf gnd-rf synch pgnd pgnd pgnd pgnd pgnd synch synch vin_pin vin_pin rst rst vout ss_inh vs1 vs2 pgnd r24 120r 0603 r25 51r 0603 tp5 vs r8 110k 0603 r12 1k 0603 jp5 c16 4.7uf x5r 1206 50v r13 dnm 1206 c9 10uf x5r 1206 50v tp1 ss/inh tp7 gnd c15 4.7uf x5r 1206 50v c2 1uf x7s 0805 100v r4 0r 0603 jp4 tp4 vout r10 dnm 0603 c23 6.8nf x7r 0603 100v l2 4.7uh xal40 c4 2.2pf cog/np0 0603 50v r18 51r 0603 r5 dnm 0603 jp3 r11 10k 0603 j1 bnc-sma-fem-180-smd 1 2 jp1 r9 dnm 0603 j2 bnc-sma-fem-180-smd 1 2 c21 6.8nf x7r 0603 100v r28 51r 0603 c17 dnm 0805 c14 4.7uf x5r 1206 50v r17 51r 0603 c22 6.8nf x7r 0603 100v + c13a 220uf 10x10 50v r27 120r 0603 r21 51r 0603 c8 150pf cog/np0 0603 50v r15 120r 0603 u1 a6986f5v rst 1 vcc 2 ss/inh 3 synch 4 fsw 5 mlf 6 comp 7 delay 8 fb 9 sgnd 10 pgnd 11 pgnd 12 lx 13 lx 14 vin 15 vbias 16 ep 17 j6 bnc-sma-fem-180-smd 1 2 j3 bnc-sma-fem-180-smd 1 2 c6 10nf x7r 0603 50v tp11 gnd r14 1k 0603 l3 220r 3a 0805 r16 120r 0603 tp6 gnd r29 dnm 0603 + c13b dnm 8x10 j7 bnc-sma-fem-180-smd 1 2 tp3 synch c7 dnm 0603 c20 6.8nf x7r 0603 100v r2 0r 0603 c24 6.8nf x7r 0603 100v q1 2n7002 sot23 c1 dnm 1206 tp8 vin_emi j5 bnc-sma-fem-180-smd 1 2 r19 120r 0603 tp2 rst c11 dnm 0603 c3 470nf x7r 0603 16v m1 mors2v1p 1 1 2 2 r22 51r 0603 c12 dnm 0603 jp2 r1 dnm 0603 r20 120r 0603 c19 6.8nf x7r 0603 100v c10 10uf x5r 1206 50v r3 dnm 0603 r7 0r 0603 m2 mors2v1p 1 1 2 2 l1 6.8uh xal50/xal40 c5 100nf x7r 0603 50v r26 51r 0603 tp9 vcc r23 120r 0603 tp10 gnd r6 1m 0603 c18 6.8nf x7r 0603 100v j4 bnc-sma-fem-180-smd 1 2 docid027739 rev 1 65/72 a6986f emc testing results 72 figure 59. ce 150r at vs1 test point (see figure 58 ) at 80% i load figure 60. ce 150r at vs1 test point (see figure 58 ) at 10% i load test results (continue): test case ce #1 - emission vs / i load_vout = 1.2 a -20 -10 0 10 20 30 40 50 60 70 80 90 100 0,1 1 10 100 1000 limit biss class ii global / 10-k (pk) limit biss class iii global / 12-m (pk) pk - vs1 av - vs1 [mhz] [dbv] ce - 150 ohm method - global pins dut: mode: i load_vout = 1.2a test case: emission vs (vs1) a6986f5v test case ce #2 - emission vs / i load_vout = 150ma -20 -10 0 10 20 30 40 50 60 70 80 90 100 0,1 1 10 100 1000 limit biss class ii global / 10-k (pk) limit biss class iii global / 12-m (pk) pk - vs1 av - vs1 [mhz] [dbv] ce - 150 ohm method - global pins dut: mode: i load_vout = 150ma test case: emission vs (vs1) a6986f5v a6986f5v emc testing results a6986f 66/72 docid027739 rev 1 figure 61. ce 150r at vout test point (see figure 58 ) at 80% i load figure 62. ce 150r at vout test point (see figure 58 ) at 10% i load test results (continue): test case ce # 5 - emission vout / i load_vout = 1.2a -20 -10 0 10 20 30 40 50 60 70 80 90 100 0,1 1 10 100 1000 limit biss class ii local / 8-h (pk) limit biss class iii local / 10-k (pk) pk - vout av - vout [mhz] [dbv] ce - 150 ohm method - local pins dut: mode: i load_vout = 1.2a test case: emission vout a6986f5v test case ce #6 - emission vout / i load_vout = 150ma -20 -10 0 10 20 30 40 50 60 70 80 90 100 0,1 1 10 100 1000 limit biss class ii local / 8-h (pk) limit biss class iii local / 10-k (pk) pk - vout av - vout [mhz] [dbv] ce - 150 ohm method - local pins dut: mode: i load_vout = 150ma test case: emission vout a6986f5v a6986f5v docid027739 rev 1 67/72 a6986f emc testing results 72 figure 63. ce 150r at rst test point (see figure 58 ) at 80% i load figure 64. ce 150r at rst test point (see figure 58 ) at 10% i load test results (continue): test case ce #7 - emission rst/ i load_vout = 1.2a -20 -10 0 10 20 30 40 50 60 70 80 90 100 0,1 1 10 100 1000 limit biss class ii local / 8-h (pk) limit biss class iii local / 10-k (pk) pk - rst av - rst [mhz] [dbv] ce - 150 ohm method - local pins dut: mode: i load_vout = 1.2a test case: emission rst a6986f5v a6986f5v test case ce #8 - emission rst/ i load_vout = 150ma -20 -10 0 10 20 30 40 50 60 70 80 90 100 0,1 1 10 100 1000 limit biss class ii local / 8-h (pk) limit biss class iii local / 10-k (pk) pk - rst av - rst [mhz] [dbv] ce - 150 ohm method - local pins dut: mode: i load_vout = 150ma test case: emission rst a6986f5v a6986f5v emc testing results a6986f 68/72 docid027739 rev 1 figure 65. ce 150r at ss/inh test point (see figure 58 on page 64 ) at 80% i load figure 66. ce 150r at ss/inh test point (see figure 58 ) at 10% i load test results (continue): test case ce #9 - emission ss_inh / i load_vout = 1.2a -20 -10 0 10 20 30 40 50 60 70 80 90 100 0,1 1 10 100 1000 limit biss class ii local / 8-h (pk) limit biss class iii local / 10-k (pk) pk - ss/inh av - ss/inh [mhz] [dbv] ce - 150 ohm method - local pins dut: mode: i load_vout = 1.2a test case: emission ss/inh a6986f5v a6986f5v test case ce #8 - emission rst/ i load_vout = 150ma -20 -10 0 10 20 30 40 50 60 70 80 90 100 0,1 1 10 100 1000 limit biss class ii local / 8-h (pk) limit biss class iii local / 10-k (pk) pk - rst av - rst [mhz] [dbv] ce - 150 ohm method - local pins dut: mode: i load_vout = 150ma test case: emission rst a6986f5v a6986f5v docid027739 rev 1 69/72 a6986f package information 72 11 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack specifications, grade definitions a nd product status are available at: www.st.com . ecopack is an st trademark. htssop16 package information package information a6986f 70/72 docid027739 rev 1 figure 67. htssop16 package outline . table 23. htssop16 package mechanical data symbol dimensions (mm) min. typ. max. a 1.20 a1 0.15 a2 0.80 1.00 1.05 b 0.19 0.30 c 0.09 0.20 d 4.90 5.00 5.10 d12.833.2 e 6.20 6.40 6.60 e1 4.30 4.40 4.50 e22.833.2 e0.65 l 0.45 0.60 0.75 l1 1.00 k 0.00 8.00 aaa 0.10 docid027739 rev 1 71/72 a6986f order codes 72 12 order codes 13 revision history table 24. order codes part numbers package packaging a6986f3v3 htssop16 tube A6986F3V3TR tape and reel a6986f5v tube a6986f5vtr tape and reel a6986f tube a6986ftr tape and reel table 25. document revision history date revision changes 15-apr-2015 1 initial release. a6986f 72/72 docid027739 rev 1 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2015 stmicroelectronics ? all rights reserved |
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